In modern digital world, there is a strong demand for efficient data streams processing methods. One of application areas is cybersecurity — IPsec is a suite of protocols that adds security to communication at the IP level. This paper presents principles of high-performance FPGA architecture for data streams processing on example of IPsec gateway implementation. Efficiency of the proposed solution allows to use it in networks with data rates of several Gbit/s.
The article focuses on the fractional-order backward difference, sum, linear time-invariant equation analysis, and difficulties of the fractional calculus microcontroller implementation with regard to designing a fractional-order proportional integral derivative (FOPID) controller. In opposite to the classic proportional integral derivative (PID), the FOPID controller is defined by five independent parameters. Hence, it is more customizable and, potentially, more precise on condition that the values of fractional integration and differentiation orders are properly selected. However, a number of operations and the time required to calculate the output signal continuously increase. This can be a significant problem considering the limitations of a microcontroller, including memory size and a constant sampling time of the set-up analog-to-digital (ADC) converters. In the article, three solutions are considered, and results obtained in the experiments are presented.
An application specific integrated design using Quadrature Linear Discriminant Analysis is proposed for automatic detection of normal and epilepsy seizure signals from EEG recordings in epilepsy patients. Five statistical parameters are extracted to form the feature vector for training of the classifier. The statistical parameters are Standardised Moment, Co-efficient of Variance, Range, Root Mean Square Value and Energy. The Intellectual Property Core performs the process of filtering, segmentation, extraction of statistical features and classification of epilepsy seizure and normal signals. The design is implemented in Zynq 7000 Zc706 SoC with average accuracy of 99%, Specificity of 100%, F1 score of 0.99, Sensitivity of 98% and Precision of 100 % with error rate of 0.0013/hr., which is approximately zero false detection.
The telemetry data are essential in evaluating the performance of aircraft and diagnosing its failures. This work combines the oversampling technology with the run-length encoding compression algorithm with an error factor to further enhance the compression performance of telemetry data in a multichannel acquisition system. Compression of telemetry data is carried out with the use of FPGAs. In the experiments there are used pulse signals and vibration signals. The proposed method is compared with two existing methods. The experimental results indicate that the compression ratio, precision, and distortion degree of the telemetry data are improved significantly compared with those obtained by the existing methods. The implementation and measurement of the proposed telemetry data compression method show its effectiveness when used in a high-precision high-capacity multichannel acquisition system.