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Abstract

A new time interval/frequency generator with a jitter below 5 ps is described. The time interval generation mechanism is based on a phase shifting method with the use of a precise DDS synthesizer. The output pulses are produced in a Spartan-6 FPGA device, manufactured by Xilinx in 45 nm CMOS technology. Thorough tests of the phase shifting in a selected synthesizer are performed. The time interval resolution as low as 0.3 ps is achieved. However, the final resolution is limited to 500 ps to maximize precision. The designed device can be used as a source of high precision reference time intervals or a highly stable square wave signal of frequency up to 50 MHz.
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Abstract

The paper describes the construction, operation and test results of three most popular interpolators from a viewpoint of time-interval (TI) measurement systems consisting of many tapped-delay lines (TDLs) and registering pulses of a wide-range changeable intensity. The comparison criteria include the maximum intensity of registered time stamps (TSs), the dependency of interpolator characteristic on the registered TSs’ intensity, the need of using either two counters or a mutually-complementing pair counter-register for extending a measurement range, the need of calculating offsets between TDL inputs and the dependency of a resolution increase on the number of used TDL segments. This work also contains conclusions about a range of applications, usefulness and methods of employing each described TI interpolator. The presented experimental results bring new facts that can be used by the designers who implement precise time delays in the field-programmable gate arrays (FPGA).
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Abstract

In this work, a fast 32-bit one-million-channel time interval spectrometer is proposed based on field programmable gate arrays (FPGAs). The time resolution is adjustable down to 3.33 ns (= T, the digitization/discretization period) based on a prototype system hardware. The system is capable to collect billions of time interval data arranged in one million timing channels. This huge number of channels makes it an ideal measuring tool for very short to very long time intervals of nuclear particle detection systems. The data are stored and updated in a built-in SRAM memory during the measuring process, and then transferred to the computer. Two time-to-digital converters (TDCs) working in parallel are implemented in the design to immune the system against loss of the first short time interval events (namely below 10 ns considering the tests performed on the prototype hardware platform of the system). Additionally, the theory of multiple count loss effect is investigated analytically. Using the Monte Carlo method, losses of counts up to 100 million events per second (Meps) are calculated and the effective system dead time is estimated by curve fitting of a non-extendable dead time model to the results (τNE = 2.26 ns). An important dead time effect on a measured random process is the distortion on the time spectrum; using the Monte Carlo method this effect is also studied. The uncertainty of the system is analysed experimentally. The standard deviation of the system is estimated as ± 36.6 × T (T = 3.33 ns) for a one-second time interval test signal (300 million T in the time interval).
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Abstract

Necessary and sufficient conditions for robust stability of the positive discrete-time interval system with time-delays are established. It is shown that this system is robustly stable if and only if one well de?ned positive discrete-time system with time-delays is asymptotically stable. The considerations are illustrated by numerical example.
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Abstract

Most systems used in quantum physics experiments require the efficient and simultaneous recording different multi-photon coincidence detection events. In such experiments, the single-photon gated counting systems can be applicable. The main sources of errors in these systems are both instability of the clock source and their imperfect synchronization with the excitation source. Below, we propose a solution for improvement of the metrological parameters of such measuring systems. Thus, we designed a novel integrated circuit dedicated to registration of signals from a photon number resolving detectors including a phase synchronizer module. This paper presents the architecture of a high-resolution (~60 ps) digital phase synchronizer module cooperating with a multi-channel coincidence counter. The main characteristic feature of the presented system is its ability to fast synchronization (requiring only one clock period) with the measuring process. Therefore, it is designed to work with various excitation sources of a very wide frequency range. Implementation of the phase synchronizer module in an FPGA device enabled to reduce the synchronization error value from 2.857 ns to 214.8 ps.
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Abstract

The Bulletin of the Polish Academy of Sciences: Technical Sciences (Bull.Pol. Ac.: Tech.) is published bimonthly by the Division IV Engineering Sciences of the Polish Academy of Sciences, since the beginning of the existence of the PAS in 1952. The journal is peer‐reviewed and is published both in printed and electronic form. It is established for the publication of original high quality papers from multidisciplinary Engineering sciences with the following topics preferred: Artificial and Computational Intelligence, Biomedical Engineering and Biotechnology, Civil Engineering, Control, Informatics and Robotics, Electronics, Telecommunication and Optoelectronics, Mechanical and Aeronautical Engineering, Thermodynamics, Material Science and Nanotechnology, Power Systems and Power Electronics. Journal Metrics: JCR Impact Factor 2018: 1.361, 5 Year Impact Factor: 1.323, SCImago Journal Rank (SJR) 2017: 0.319, Source Normalized Impact per Paper (SNIP) 2017: 1.005, CiteScore 2017: 1.27, The Polish Ministry of Science and Higher Education 2017: 25 points. Abbreviations/Acronym: Journal citation: Bull. Pol. Ac.: Tech., ISO: Bull. Pol. Acad. Sci.-Tech. Sci., JCR Abbrev: B POL ACAD SCI-TECH Acronym in the Editorial System: BPASTS.
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Abstract

Simple new necessary and sufficient conditions for asymptotic stability of the positive linear discrete-time systems with delays in states are established. It is shown that asymptotic stability of the system is equivalent to asymptotic stability of the corresponding positive discrete-time system without delays of the same size. The considerations are illustrated by numerical examples.
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Abstract

Accurate prediction of power load plays a crucial role in the power industry and provides economic operation decisions for the power operation department. Due to the unpredictability and periodicity of power load, an improved method to deal with complex nonlinear relation was adopted, and a short-term load forecasting model combining FEW (fuzzy exponential weighting) and IHS (improved harmonic search) algorithms was proposed. Firstly, the domain space was defined, the harmony memory base was initialized, and the fuzzy logic relation was identified. Then the optimal interval length was calculated using the training sample data, and local and global optimum were updated by optimization criteria and judging criteria. Finally, the optimized parameters obtained by an IHS algorithm were applied to the FEW model and the load data of the Huludao region (2013) in Northeast China in May. The accuracy of the proposed model was verified using an evaluation criterion as the fitness function. The results of error analysis show that the model can effectively predict short-term power load data and has high stability and accuracy, which provides a reference for application of short-term prediction in other industrial fields.
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Abstract

An embedded time interval data acquisition system (DAS) is developed for zero power reactor (ZPR) noise experiments. The system is capable of measuring the correlation or probability distribution of a random process. The design is totally implemented on a single Field Programmable Gate Array (FPGA). The architecture is tested on different FPGA platforms with different speed grades and hardware resources. Generic experimental values for time resolution and inter-event dead time of the system are 2.22 ns and 6.67 ns respectively. The DAS can record around 48-bit x 790 kS/s utilizing its built-in fast memory. The system can measure very long time intervals due to its 48-bit timing structure design. As the architecture can work on a typical FPGA, this is a low cost experimental tool and needs little time to be established. In addition, revisions are easily possible through its reprogramming capability. The performance of the system is checked and verified experimentally.
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