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Abstract

This work depicts the effects of deep cryogenically treated high-speed steel on machining. In recent research, cryogenic treatment has been acknowledged for improving the life or performance of tool materials. Hence, tool materials such as the molybdenum-based high-speed tool steel are frequently used in the industry at present. Therefore, it is necessary to observe the tool performance in machining; the present research used medium carbon steel (AISI 1045) under dry turning based on the L9 orthogonal array. The effect of untreated and deep cryogenically treated tools on the turning of medium carbon steel is analyzed using the multi-input-multi-output fuzzy inference system with the Taguchi approach. The cutting speed, feed rate and depth of cut were the selected process parameters with an effect on surface roughness and the cutting tool edge temperature was also observed. The results reveal that surface roughness decreases and cutting tool edge temperature increases on increasing the cutting speed. This is followed by the feed rate and depth of cut. The deep cryogenically treated tool caused a reduction in surface roughness of about 11% while the cutting tool edge temperature reduction was about 23.76% higher than for an untreated tool. It was thus proved that the deep cryogenically treated tool achieved better performance on selected levels of the turning parameters.
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Abstract

This paper describes the arithmetic blocks based on Montgomery Multiplier (MM), which reduces complexity, gives lower power dissipation and higher operating frequency. The main objective in designing these arithmetic blocks is to use modified full adder structure and carry save adder structure that can be implemented in algorithm based MM circuit. The conventional full adder design acts as a benchmark for comparison, the second is the modified Boolean equation for full adder and third design is the design of full adder consisting of two XOR gate and a 2-to-1 Multiplexer. Besides Universal gates such as NOR gate and NAND gate, full adder circuits are used to further improve the speed of the circuit. The MM circuit is evaluated based on different parameters such as operating frequency, power dissipation and area of occupancy in FPGA board. The schematic designs of the arithmetic components along with the MM architecture are constructed using Quartus II tool, while the simulation is done using Model sim for verification of circuit functionality which has shown improvement on the full adder design with two XOR gate and one 2-to-1 Multiplexer implementation in terms of power dissipation, operating frequency and area.
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