The paper presents modification of the method dedicated to a complex area decomposition of a set of logic functions whereas the altered method is dedicated to implement the considered logic circuits within FPGA structures. The authors attempted to reach solutions where the number of configurable logic blocks and the number of structural layer would be reasonably balanced on the basis of the minimization principle. The main advantage of the procedure when the decomposition is carried out directly on the BDD diagram is the opportunity of immediate checking whether the decomposed areas of the diagram do not exceed the resources of logic blocks incorporated into the integrated circuits that are used for implementation of the logic functions involved.
In modern digital world, there is a strong demand for efficient data streams processing methods. One of application areas is cybersecurity — IPsec is a suite of protocols that adds security to communication at the IP level. This paper presents principles of high-performance FPGA architecture for data streams processing on example of IPsec gateway implementation. Efficiency of the proposed solution allows to use it in networks with data rates of several Gbit/s.
This paper describes the arithmetic blocks based on Montgomery Multiplier (MM), which reduces complexity, gives lower power dissipation and higher operating frequency. The main objective in designing these arithmetic blocks is to use modified full adder structure and carry save adder structure that can be implemented in algorithm based MM circuit. The conventional full adder design acts as a benchmark for comparison, the second is the modified Boolean equation for full adder and third design is the design of full adder consisting of two XOR gate and a 2-to-1 Multiplexer. Besides Universal gates such as NOR gate and NAND gate, full adder circuits are used to further improve the speed of the circuit. The MM circuit is evaluated based on different parameters such as operating frequency, power dissipation and area of occupancy in FPGA board. The schematic designs of the arithmetic components along with the MM architecture are constructed using Quartus II tool, while the simulation is done using Model sim for verification of circuit functionality which has shown improvement on the full adder design with two XOR gate and one 2-to-1 Multiplexer implementation in terms of power dissipation, operating frequency and area.
The paper presents a solution of the control system for fatigue test stand MZGS-100 PL, comprising the integrated Real-Time controller based on FPGA (Field-Programmable Gate Array) technology with LabVIEW software. The described control system performs functions such as continuous regulation of speed induction motor, measuring strain of the lever machine and the test specimen, displacement of the polyharmonic vibrator, as well as the elimination of interferences, overload protection and emergency stop of the machine. The fatigue test stand also allows to set the pseudo-random history of energy parameter W(t).
Mitigation of electromagnetic inference (EMI) is currently a challenge for scientists and designers in order to cope with electromagnetic compatibility (EMC) compliance in switching mode power supply (SMPS) and ensure the reliability of the whole system. Standard filtering techniques: passive and active ones present some insufficiency in terms of performance at high frequencies (HF) because analog components would no longer be controllable and this is mainly due to their parasitic elements. So developing EMI digital filters is very interesting, especially with the embedment of a machine control system on a field programmable gate array (FPGA) chip. In this paper, we present a design of an active digital EMI filter (ADF) to be integrated in a drive train system of an electric vehicle (EV). Hardware design as well as FPGA implementation issues have been presented to prove the efficiency of the developed digital filtering structure.
The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control, diagnostic and telemetric system for a large industrial object. An example of system implementation is the European TESLA-XFEL accelerator. The free electron laser is expected to work in the VUV region now and in the range of X-rays in the future. The design of a system based on the FPGA circuits and multi-gigabit optical network is discussed. The system design approach is fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of DSP/PC enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. The current parameters of the system model, under the design, are presented. The considerations are shown on the background of the system application in the hostile industrial environment. The work is a digest of a few development threads of the hybrid, optoelectronic, telemetric networks (HOTN). In particular, the outline of construction theory of HOTN node was presented as well as the technology of complex, modular, multilayer HOTN system PCBs. The PCBs contain critical sub-systems of the node and the network. The presented exemplary sub-systems are: fast optical data transmission of 2.5 Gbit/s, 3.125 Gbit/s and 10 Gbit/s; fast A/C and C/A multichannel data conversion managed by FPGA chip (40 MHz, 65 MHz, 105 MHz), data and functionality concentration, integration of floating point calculations in the DSP units of FPGA circuit, using now discrete and next integrated PC chip with embedded OS; optical distributed timing system of phase reference; and 1GbEth video interface (over UTP or FX) for CCD telemetry and monitoring. The data and functions concentration in the HOTN node is necessary to make efficient use of the multigigabit optical fiber transmission and increasing the processing power of the FPGA/DSP/PC chips with optical I/O interfaces. The experiences with the development of the new generation of HOTN node based on the new technologies of data and functions concentration are extremely promising, because such systems are less expensive and require less labour.
A new time interval/frequency generator with a jitter below 5 ps is described. The time interval generation mechanism is based on a phase shifting method with the use of a precise DDS synthesizer. The output pulses are produced in a Spartan-6 FPGA device, manufactured by Xilinx in 45 nm CMOS technology. Thorough tests of the phase shifting in a selected synthesizer are performed. The time interval resolution as low as 0.3 ps is achieved. However, the final resolution is limited to 500 ps to maximize precision. The designed device can be used as a source of high precision reference time intervals or a highly stable square wave signal of frequency up to 50 MHz.
The paper describes the construction, operation and test results of three most popular interpolators from a viewpoint of time-interval (TI) measurement systems consisting of many tapped-delay lines (TDLs) and registering pulses of a wide-range changeable intensity. The comparison criteria include the maximum intensity of registered time stamps (TSs), the dependency of interpolator characteristic on the registered TSs’ intensity, the need of using either two counters or a mutually-complementing pair counter-register for extending a measurement range, the need of calculating offsets between TDL inputs and the dependency of a resolution increase on the number of used TDL segments. This work also contains conclusions about a range of applications, usefulness and methods of employing each described TI interpolator. The presented experimental results bring new facts that can be used by the designers who implement precise time delays in the field-programmable gate arrays (FPGA).
In this work, a fast 32-bit one-million-channel time interval spectrometer is proposed based on field programmable gate arrays (FPGAs). The time resolution is adjustable down to 3.33 ns (= T, the digitization/discretization period) based on a prototype system hardware. The system is capable to collect billions of time interval data arranged in one million timing channels. This huge number of channels makes it an ideal measuring tool for very short to very long time intervals of nuclear particle detection systems. The data are stored and updated in a built-in SRAM memory during the measuring process, and then transferred to the computer. Two time-to-digital converters (TDCs) working in parallel are implemented in the design to immune the system against loss of the first short time interval events (namely below 10 ns considering the tests performed on the prototype hardware platform of the system). Additionally, the theory of multiple count loss effect is investigated analytically. Using the Monte Carlo method, losses of counts up to 100 million events per second (Meps) are calculated and the effective system dead time is estimated by curve fitting of a non-extendable dead time model to the results (τNE = 2.26 ns). An important dead time effect on a measured random process is the distortion on the time spectrum; using the Monte Carlo method this effect is also studied. The uncertainty of the system is analysed experimentally. The standard deviation of the system is estimated as ± 36.6 × T (T = 3.33 ns) for a one-second time interval test signal (300 million T in the time interval).
The designing process of high resolution time interval measurement systems creates many problems that need to be eliminated. The problems are: the latch error, the nonlinearity conversion, the different duty cycle coefficient of the clock signal, and the clock signal jitter. Factors listed above affect the result of measurement. The FPGA (Field Programmable Gate Array) structure also imposes some restrictions, especially when a tapped delay line is constructed. The article describes the high resolution time-to-digital converter, implemented in a FPGA structure, and the types of errors that appear there. The method of minimization and processing of data to reduce the influence of errors on the measurement is also described.
Based on the publications regarding new or recent measurement systems for the tokamak plasma experiments, it can be found that the monitoring and quality validation of input signals for the computation stage is done in different, often simple, ways. In the paper is described the unique approach to implement the novel evaluation and data quality monitoring (EDQM) model for use in various measurement systems. The adaptation of the model is made for the GEM-based soft X-ray measurement system FPGA-based. The EDQM elements has been connected to the base firmware using PCI-E DMA real-time data streaming with minimal modification. As additional storage, on-board DDR3 memory has been used. Description of implemented elements is provided, along with designed data processing tools and advanced simulation environment based on Questa software.
An embedded time interval data acquisition system (DAS) is developed for zero power reactor (ZPR) noise experiments. The system is capable of measuring the correlation or probability distribution of a random process. The design is totally implemented on a single Field Programmable Gate Array (FPGA). The architecture is tested on different FPGA platforms with different speed grades and hardware resources. Generic experimental values for time resolution and inter-event dead time of the system are 2.22 ns and 6.67 ns respectively. The DAS can record around 48-bit x 790 kS/s utilizing its built-in fast memory. The system can measure very long time intervals due to its 48-bit timing structure design. As the architecture can work on a typical FPGA, this is a low cost experimental tool and needs little time to be established. In addition, revisions are easily possible through its reprogramming capability. The performance of the system is checked and verified experimentally.