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A new simple design methodology which makes LDR output nearly insensitive to jumps of the load current for long times is proposed. This methodology is tested for more than 104 seconds. Our procedure leans on cross coupling of the time second derivative of the LDR power transistor gate and drain voltages along with their currents. This technique keeps low values of these currents in order of nano or hundreds of micro amperes for undershot or overshot cases, respectively. The introduced methodology has been applied to a standard CMOS of 0.18μm technology for NMOS transistors and validated using MATLAB R2014a.
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